The patent documents listed below disclose technologies for sharing a memory such as an SDRAM (Synchronous Dynamic Random Access Memory).
Patent document 1 discloses technology in which, in a case where a plurality of data processing apparatuses that each include a CPU (Central Processing Unit) etc. are accessing a single shared SDRAM, selective switching is performed to determine the data processing apparatus that is to access the SDRAM. The technology of patent document 1 prevents malfunctions in the SDRAM due to an unstable condition that occurs when the supply of a control signal to the SDRAM is stopped during switching of the data processing apparatuses, thereby enabling the data processing apparatuses to stably access the SDRAM.
Patent document 2 discloses technology for improving the utilization efficiency of a data bus when a plurality of processors accesses a synchronous DRAM. In the technology of patent document 2, timeslots in which the processors can perform access are set in advance, and each processor accesses the synchronous DRAM during the corresponding time slot.
Also, there is technology in which, in a case where a plurality of processors etc. are implemented on a single integrated circuit and share an SDRAM, when access requests have been output from the processors etc., commands and addresses pertaining to the access requests are sequentially input to the SDRAM in accordance with a preset arbitration rule that indicates an order in which the processors etc. are to access the SDRAM. This technology takes into account the fact that when an input of read or write commands and addresses are received from the processors etc., the SDRAM waits until a predetermined number of clock cycles have elapsed before reading or writing data. In this technology, data transfer is performed in uninterrupted succession by receiving an input of a command and address before data reading or writing pertaining to the previous command and address has been completed, thereby improving the utilization efficiency of the data bus.
Patent document 1: Japanese Patent Application Publication No. 2004-102779
Patent document 2: Japanese Patent Application Publication No. H07-311730